1. Field of the Invention
The present invention relates to the field of fault detection, and more particularly to fault detection and protection of analog switches and devices incorporating analog switches, such as by way of example, multiplexers and the like.
2. Prior Art
Integrated circuit analog switches, derived from CMOS technology, have been well known for many years. As shown in FIG. 1, such switches are generally characterized by a P-channel enhancement mode device and an N-channel enhancement mode device connected in parallel and having their gates driven by a digital (two state) control signal and its complement, respectively. This arrangement of complementary devices and complementary drive turns the devices on and off in unison, and when on, couples the input to the switch to the output of the switch through a low impedance, regardless of the analog level of the input. In particular, the complementary devices and complementary drive provides a symmetry assuring that when the switch is on, one device is firmly on regardless of which power supply rail the input and output signals may be approaching. Such an arrangement of devices and drive is the prevalent way switches are made today.
CMOS switches can be made using a variety of process technologies (i.e., dielectric isolation, trench isolation, and standard junction isolation). While each process has its own advantages and disadvantages, a universal problem is what happens to the final switch product under fault conditions. This has a major reliability effect on a customer's system, as it is highly preferable that a fault will cause no more than a temporary malfunction recoverable when the fault disappears or is corrected, rather than a catastrophic failure requiring parts or subsystem replacement before the board or system is operative again.
Normal operation of CMOS analog switches is limited to the power supplies applied to the part or lower, depending upon the individual device sold. For example, with plus and minus 15 v power supplies, many analog switches can handle input signals up to plus and minus 15 v. As long as users stay within the power supply range, the parts perform to the data sheets describing the parts. However, if input signals exceed the power supplies (fault condition), or the power supplies are inadvertently turned off while signals are present (fault condition), the part may be destroyed because of the forward biasing, from a relatively low impedance source, of the diodes formed between diffused regions and the substrate or wells in the substrate which are connected to one or the other power supply connections. Even if the switch is not destroyed, it may conduct the fault condition to its output and the device connected to the output may be damaged. For these reasons, manufacturers often warn against allowing this condition to occur.
Either fault condition can not only destroy the analog switch, but can also destroy the circuitry following the switch. While nobody plans on these faults occurring in a system, they do with enough frequency to make it a substantial reliability problem. Junction isolated CMOS switches are the predominant type sold today and most exhibit a sequencing problem during normal testing. This sequencing problem is really related to one of the fault conditions listed above, namely one of the power supplies being off while signals are present. In a typical N-substrate, junction-isolated, CMOS switch, the substrate must be taken to the most positive voltage in the circuit, and this is normally taken to the positive power supply voltage (i.e., +15 v for plus and minus 15 v supply systems). Any P-diffusion made into this substrate must have voltages no higher than the positive supply value, or device damage can occur. The mechanism for this is the P/N junction formed by the P diffusion into the N-substrate. This forms a diode with the cathode of the diode being the N material, and the anode of the diode being the P diffusion. This junction will be forward-biased whenever the anode terminal is about 0.6 v or higher with respect to the cathode terminal. Now with the N-substrate at plus 15 v, the P diffusion voltage can be no higher than 15 v+0.6 v=15.6 v, or alternately, if the normal 15 v supply is off (and thus is at Ground potential, or 0 v), then the P diffusion voltage can be no higher than 0 v+0.6 v=0.6 v.
For normal operation, such switches can handle any signal within the power supply range with no damage to the switches. If a sequence occurs that has a 0.6 v or more signal applied while the positive supply has not yet been applied, a fault condition is present, and damage will probably be the result. Switches can be damaged if the positive and/or negative supply turn-ons lag the signal turn-on by as little as microseconds. Thus, any test equipment setup must turn on the most positive supply first, and then the remaining voltages can be applied. While a controlled test environment can be programmed this way, field use of equipment has been a more difficult problem.
A similar situation occurs when N-channels are made by diffusing a P-well into the N-substrate, and subsequent N diffusions are made into the P-well. If the P-well (body of the N-channel) is taken to the most negative voltage, which is common, then the source or drain (N diffusions into the P-well) must never be more negative than 0.6 v relative to the P-well voltage. For a plus and minus 15 v supply system, this means the N-channel body would go to -15 v, and the source or drain cannot go less than -15.6 v or damage probably will result. As in the 15 v case just described, if the -15 v power supply inadvertently goes off while negative signals are present at the source or drain of an N-channel device, these negative signals must be below -0.6 v or so, or damage can result. In this case, the diode is formed by the N diffusion in the P-well.
There is a partial solution to the fault conditions already existing in the industry; that is to use a serial configuration of N-channel, P-channel, N-channel devices. Indeed, this will prevent any of the described faults from destroying devices. However this scheme has the disadvantage of not handling signals up to the supply values (switching them through), as this will only switch signals less than the supply values by virtue of the thresholds of the individual N and P channel devices (i.e., for typical 1.5 v thresholds for either N or P channel devices, only 15 v-1.5 v=13.5 v can be switched through the circuits). This is a disadvantage to some users of the switches. Also, the chip area used to assure that the "on" resistance for the switch is below a guaranteed maximum value using a series configuration is much greater than that used to make a parallel combination of an N and P channel. This has a large impact on final chip size, and the selling price of the part.
Until now, the best solution for fault protection has been the use of the series N,P,N channel structures, while the most economical circuits have used parallel N and P channel structures, but these have suffered with the fault conditions described.